DS26502DK
FPGA ID Registers
BID: BOARD ID (Offset = 0x0000)
BID is read only with a value of 0xD.
XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset = 0x0002)
XBIDH is read only with a value of 0x0.
XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset = 0x0003)
XBIDM is read only with a value of 0x1.
XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset = 0x0004)
XBIDL is read only with a value of 0x6.
BREV: BOARD FAB REVISION (Offset = 0x0005).
BREV is read only and displays the current fab revision.
AREV: BOARD ASSEMBLY REVISION (Offset = 0x0006)
AREV is read only and displays the current assembly revision.
PREV: PLD REVISION (Offset = 0x0007)
PREV is read only and displays the current PLD firmware revision.
FPGA Status Registers
Register Name: BUSMO
Register Description: DS26502 Bus Mode
Register Offset: 0x0011
Bit #
Name
Default
7
LevCPOL
6
LevCPHA
5
HW
4
SPI
3
INMUX
2
IMUX
1
MNMUX
0
MMUX
The FPGA derives values in the BUSMO register from the levels present at the DS26502 pins.
Bit 7: LevCPOL. When set the DS26502 CPOL pin is high. Note: This pin is called A3/CPOL/L1 in
parallel/serial/hardware modes.
Bit 6: LevCPHA. When set the DS26502 CPHA pin is high. Note: This pin is called A2/CPHA/L0 in
parallel/serial/hardware modes.
Bit 5: HW. When set the DS26502 is in hardware mode.
Bit 4: SPI. When set the DS26502 is in SPI (3-wire) mode.
Bit 3: INMUX. When set the DS26502 is in Intel nonmultiplexed mode.
Bit 2: IMUX. When set the DS26502 is in Intel multiplexed mode.
Bit 1: MNMUX. When set the DS26502 is in Motorola nonmultiplexed mode.
Bit 0: MMUX. When set the DS26502 is in Motorola multiplexed mode.
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相关PDF资料
DS26503DK KIT DESIGN FOR DS26503
DS26504DK KIT DESIGN FOR DS26504
DS26519DK KIT DEMO FOR DS26519
DS26521DK KIT DESIGN FOR DS26521
DS3106DK KIT DEMO FOR DS3106
DS3144DK KIT DEMO FOR DS3144
DS3150DK KIT DEMO DS3150 DS3/E3/STS-2 LIU
DS3153DK KIT DEMO FOR DS3153
相关代理商/技术参数
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